A parallel processor has a plurality of operation units that execute
operation instructions, and a multi-bank register file in which a
plurality of banks each having a plurality of registers are formed. Each
of machine instructions, which are input simultaneously, is split into a
plurality of nano-instructions each of which includes at least one of an
access instruction and operation instruction. The output clock cycles of
operation instructions with respect to the operation units are
arbitrated. Furthermore, the output clock cycles of access instructions
to the multi-bank register file are arbitrated so as to prevent access
instructions from contending in an identical bank in the multi-bank
register file.