The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The manufacturing method comprises the steps of: providing a semiconductor substrate (1) having an upper surface (O) and having first and second transistor regions (T1, T2); wherein said first transistor region (T1) is a n-MOSFET region and second transistor region (T2) is a p-MOSFET region; forming a gate structure on said first and second transistor region (T1, T2) including at least one gate dielectric layer (2, 3, 10c, 17, 25) and one gate layer (4; 35; 50, 60) in each of said first and second transistor regions (T1, T2); wherein said gate layer (4; 35; 60) in said second transistor region (T2) is made of negatively doped polysilicon; wherein said at least one gate dielectric layer (2, 10c, 17) in said first transistor region (T1) comprises a first dielectric layer (2, 10c, 17); wherein said at least one gate dielectric layer (2, 3, 10c, 25, 25') in said second transistor region (T2) comprises an interfacial dielectric layer (2; 25; 25') located adjacent to said gate layer (4; 35; 60) in said second transistor region (T2), which interfacial dielectric layer (2; 25; 25') forms an Al.sub.2O.sub.3 containing interface on said gate layer (4; 35; 60) in said second transistor region (T2) causing a Fermi-pinning effect; and wherein said first transistor region (T1) does not include said interfacial dielectric layer (2; 25; 25').