A thin film transistor array panel is provided, which includes: a gate wire formed on an insulating substrate; a data wire formed on the insulating substrate, insulated from the gate wire, and intersecting the gate wire; a storage electrode wire formed on the insulating substrate, insulated from the data wire, and intersecting the data wire; a plurality of pixel electrodes provided on the respective pixel areas defined by the intersections of the gate wire and the data wire, each pixel electrode having a cutout; a plurality of direction control electrodes provided on the respective pixel areas defined by the intersections of the gate wire and the data wire; a plurality of first thin film transistors connected to the gate wire, the data wire, and the pixel electrodes; and a plurality of second thin film transistors connected to the gate wire, the storage electrode wire, and the direction control electrodes.