A semiconductor memory device includes a mode setting register for generating a parallel bit test signal and a code according to an externally applied mode setting register code in response to a mode setting command; a data input circuit for receiving and outputting at least one bit of externally applied data in response to a write command; and a test pattern data generating circuit for receiving the parallel bit test signal and a predetermined bit from the code to generate a test pattern data in response to the at least one bit of externally applied data received from the data input circuit.