The present invention discloses a circuit for generating a wait signal in a semiconductor device. Even if an address input enable signal is synchronized with a clock and continuously or irregularly inputted, the circuit for generating the wait signal in the semiconductor device generates the wait signal suitable for a latency counter by using the finally-inputted address input enable signal. In addition, the circuit for generating the wait signal in the semiconductor device generates the wait signals having various pulse widths to be suitable for various latency counters, and enables the object wait signal earlier than data input or output by one clock, or simultaneously with data input or output.