A lead frame (10) for a semiconductor device includes a first row of terminals (12) surrounding a die receiving area (14) and a second row of terminals (16) spaced from and surrounding the first row of terminals (12). The first and second rows of terminals (12, 16) have a first height (H.sub.1). The terminals (12) of the first row include a step (26) that has a greater height (H.sub.2). Bond wires (36) connecting die pads (34) to the first row terminals (12) extend over the second height H.sub.2 part of the terminal (12) and are attached to the first height H.sub.1 part of the terminal (12). The step (26) insures that the bond wires (36) attached to the stepped terminals (12) have a high wire kink profile so that they are less susceptible to damage in later process steps.