Nonplanar device with stress incorporation layer and method of fabrication

   
   

A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

 
Web www.patentalert.com

< Metal spacer gate for CMOS FET

< Bonded wafer with metal silicidation

> Semiconductor structure having buried track conductors, and method for generating an electrical contact with buried track conductors

> Sacrificial annealing layer for a semiconductor device and a method of fabrication

~ 00189