A semiconductor memory device according to the present invention includes: a
plurality
of N-ch MOS transistors arranged in an area surrounding a plurality of memory cells
arranged in an array, at a spacing depending on a spacing of the plurality of memory
cells, for driving the plurality of memory cells; and a plurality of dummy transistors
32-j each of which is formed between two adjacent ones of the plurality
of N-ch MOS transistors 30-k so as to share diffusion layers with
adjacent N-ch MOS transistors 30 and each of which has a gate electrode
supplied with a voltage for electrically insulating these adjacent transistors
30-k.
