A semiconductor device includes a non-volatile memory transistor 100.
An
interlayer dielectric layer 40 is provided on a semiconductor layer 10
where the non-volatile memory transistor 100 is formed. The interlayer
dielectric layer 40 is an insulation layer for electrically isolating a
conductive layer 30 formed over the semiconductor layer 10 from the
non-volatile memory transistor, and includes a layer 42 containing nitride.
