A method for optimizing an algorithm specified for implementation on an integrated circuit for a specified application. The algorithm is analyzed with respect to its performance, and estimates of implementation area and speed are calculated. Specifically, the degrees of freedom for the algorithm alternations under specific targeted implementation objective functions and constraints are identified. The algorithm solution space is then searched to identify the algorithm structure that is best suited for the specified design goals and constraints. Algorithm parameters which satisfy performance metrics and can be implemented with minimum silicon area are identified.