A four-bit FinFET memory cell, method of fabricating four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.