A floating gate transistor is formed by simultaneously creating buried contact
openings on both EEPROM transistor gates and DRAM access transistor source/drain
diffusions. Conventional DRAM process steps are used to form cell storage capacitors
in all the buried contact openings, including buried contact openings on EEPROM
transistor gates. An EEPROM transistor gate and its associated cell storage capacitor
bottom plate together forms a floating gate completely surrounded by insulating
material. The top cell storage capacitor plate on an EEPROM transistor is used
as a control gate to apply programming voltages to the EEPROM transistor. Reading,
writing, and erasing the EEPROM element are analogous to conventional floating-gate
tunneling oxide (FLOTOX) EEPROM devices. In this way, existing DRAM process steps
are used to implement an EEPROM floating gate transistor nonvolatile memory element.
