A field effect transistor (FET), integrated circuit (IC) chip including the FETs
and a method of forming the FETS. The devices have a thin channel, e.g., an ultra-thin
(smaller than or equal to 10 nanometers (10 nm)) silicon on insulator (SOI) layer.
Source/drain regions are located in recesses at either end of the thin channel
and are substantially thicker (e.g., 30 nm) than the thin channel. Source/drain
extensions and corresponding source/drain regions are self aligned to the FET gate
and thin channel.
